1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and more particularly, to a fabrication method of a semiconductor device with a Silicon On Insulator (SOI) structure that provides better radiation of heat and reduces the parasitic capacitance between a wiring or interconnecting conductor and a semiconductor substrate.
2. Description of the Prior Art
Conventionally, the selective oxidation technique was used for isolation purpose in fabrication of bipolar large-scale integrated circuits (LSIs) formed on a silicon (Si) substrate.
FIG. 1 shows an npn bipolar transistor fabricated by using the selective oxidation technique, in which only one device region is drawn for the sake of simplification.
In FIG. 1, an n-type single-crystal Si layer 33 formed on a p-type single-crystal Si substrate 31 is partitioned by a silicon dioxide (SiO.sub.2) film 38, defining device regions 35 and a remaining non-device region 36 on the substrate 31. The SiO.sub.2 film 38 is selectively formed using a mask (not shown) which is typically made of a patterned silicon nitride (Si.sub.3 O.sub.4) film. The device regions 35 are laterally isolated by the SiO.sub.2 film 38 from each other.
The single-crystal Si layer 33 is made of a lower sublayer and an upper sublayer. The lower sublayer forms n+-type buried regions 33a, and the upper sublayer contains n-type collector regions 33e, p-type base regions 33d and n-type emitter regions 33c in the device regions 35.
The conventional selective oxidation technique was not able to satisfactorily cope with the progressing miniaturization of the elements and therefore, the following trench isolation technique was then developed.
FIG. 2 shows an npn bipolar transistor fabricated by using the trench isolation technique, in which an n-type single-crystal Si layer 43 formed on a p-type single-crystal Si substrate 41 is partitioned by trenches, defining device regions 45 and a remaining a non-device region 46 on the substrate 41. The trenches surround the corresponding device regions 45, respectively, and extend vertically from the surface of the layer 43 to the inside of the substrate 41. The trenches are filled with an insulator 48 such as SiO.sub.2. The device regions 45 are laterally isolated by the insulator 48 from each other.
In the device regions 45, similar to the case of FIG. 1, the single-crystal Si layer 43 is made of a lower sublayer and an upper sublayer. The lower sublayer forms n+-type buried regions 43a, and the upper sublayer contains n+-type collector regions 43e, p-type base regions 43d and n-type emitter regions 43c in the device regions 45.
Recently, high-quality SOI structures have become able to be acquired readily because the Separation by IMplanted OXygen (GIMOX) technique and the wafer bonding technique have been developed. FIG. 3 shows an npn bipolar transistor fabricated by using such a SOI structure.
In FIG. 3, the SOI structure contains an n-type single-crystal Si layer 53, a single-crystal Si substrate 51 and an SiO.sub.2 layer 52 placed between the substrate 51 and the layer 53.
The single-crystal Si layer 53 is partitioned by trenches to define device regions 55 and a remaining a non-device region 56 on the SiO.sub.2 layer 52. The trenches surround the corresponding device regions 55, respectively, and extend vertically from the surface of the Si layer 53 to the SiO.sub.2 layer 52. The trenches are filled with an insulator 58 such as SiO.sub.2.
Similar to the cases of FIGS. 1 and 2, the single-crystal Si layer 53 is made of a lower sublayer and an upper sublayer. The lower sublayer forms n+-type buried regions 53a, and the upper sublayer contains n-type collector regions 53e, p-type base regions 53d and n-type emitter regions 53c in the device regions 55.
The device regions 55 are laterally isolated by the insulator 58 and vertically isolated by the underlying SiO.sub.2 layer 52 from each other. This means that the complete isolation of the device regions 55 can be realized.
With the conventional bipolar transistor shown in FIG. 3, the device regions 55 are laterally and vertically isolated by the insulators 58 and 52 and therefore, there is an advantage that improved isolation reliability can be obtained compared with the cases of the above selective oxidation and trench isolation techniques.
Another advantage is that the transistor of FIG. 3 is capable of high-speed operation, the reason of which is as follows:
In the transistor of FIG. 1, parasitic capacitances occur between the collector regions 33e and the substrate 31. In the transistor of FIG. 2, parasitic capacitances occur between the collector regions 43e and the substrate 41. On the other hand, in the transistor of FIG. 3, parasitic capacitances between the single-crystal Si layer 53 of the non-device region 56 and the substrate 51 occurs, which changes dependent upon the thickness of the intervening SiO.sub.2 layer 52. If the thickness of the layer 52 is about 0.2 .mu.m or more, the parasitic capacitance of the transistor of FIG. 3 becomes lower than the cases of FIGS. 1 and 2, resulting in the higher-speed operation.
In the case of the transistor of FIG. 3, the isolation process is, which is similar to that of the trench isolation of FIG. 2, performed by the popular photolithography and dry etching techniques. The trench formation process is readily realized by utilizing the etching selectivity between Si and SiO.sub.2. Also, the SiO.sub.2 filling process into the trenches is realized by the same process in the case of the conventional trench isolation of FIG. 2.
Thus, in the case of the SOI structure of FIG. 3, the complete isolation structure can be obtained without substantial change in fabrication process with respect to the conventional trench isolation structure of FIG. 2.
However, the SOI structure of FIG. 3 has a disadvantage of higher parasitic capacitances between the wiring or interconnecting conductors and the substrate 51 than the case of the conventional selective oxidation technique of FIG. 1. The reason for the higher parasitic capacitance is that the non-device region 56 has the single-crystal Si layer 53 that is doped with an impurity to act as a conductor, instead of the insulating SiO.sub.2 film 38.
To overcome such the capacitance problem, another structure was developed, in which the selective oxidation technique was additionally performed in the structure of FIG. 3. However, this structure is not practically because a great stress tends to be applied to the substrate 51 due to the SiO.sub.2 layer placed in the non-device region 56.
Then, a further structure shown in FIG. 4 was developed, which was disclosed by Nishizawa et al. in "1991 Symposium on VLSI Technology Digest", pp 51-52.
In FIG. 4, the SOI structure contains an n-type single-crystal Si layer 63, a single-crystal Si substrate 61 and an SiO.sub.2 layer 62 placed between the substrate 61 and the layer 63.
The single-crystal Si layer 63 is partitioned by deep trenches to define device regions 65 and a remaining a non-device region 66 on the SiO.sub.2 layer 62. The trenches surround the corresponding device regions 65, respectively. The trenches are filled with an insulator 68 such as SiO.sub.2. The device regions 65 are laterally isolated by the insulator 68 and vertically isolated by the underlying SiO.sub.2 layer 62 from each other.
Similar to the cases of FIGS. 1, 2 and 3, the single-crystal Si layer 63 is made of a lower sublayer and an upper sublayer. The lower sublayer forms n+-type buried regions 63a, and the upper sublayer contains n-type collector regions 63e, p-type base regions 63d and n-type emitter regions 63c in the device regions 65.
To reduce the parasitic capacitances, shallow trenches are formed on the single-crystal Si layer 63. Therefore, unlike the SOI structure of FIG. 3, the Si layer 63 in the non-device region 66 is reduced in thickness, and the insulator 68 is placed not only to fill the isolating deep trenches but also the capacitance-reducing shallow trenches on the Si layer 63. Thus, both the satisfactory isolation and parasitic capacitance reduction can be realized.
However, the SOI structure of FIG. 4 has a disadvantages that the parasitic capacitances between the wiring or interconnecting conductors and the substrate 61 are still large due to the single-crystal Si layer 63 placed in the non-device region 66, and that the number of necessary fabrication process steps is large because the deep and shallow trenches are necessary. To overcome these disadvantages, the inventor, M. Sugiyama, has developed the other SOI structure as shown in FIGS. 5, 6 and 7A to 7D, which was disclosed in 1994 in the Japanese Non-Examined Patent Publication No. 6-177235.
The SOI structure of FIG. 5 contains an n-type single-crystal Si layer 73, a single-crystal Si substrate 71, and an SiO.sub.2 layer 72 placed between the substrate 71 and the layer 73.
The single-crystal Si layer 73 is selectively etched to be islands, defining device regions 75 by the islands and a remaining a non-device region 76 on the SiO.sub.2 layer 72. The SiO.sub.2 layer 72 is exposed in the non-device region 76 from the layer 73 and is covered with an SiO.sub.2 film 78.
In the device regions 75, similar to the cases of FIGS. 1, 2, 3 and 4, the single-crystal Si layer 73 is made of a lower sublayer and an upper sublayer. The lower sublayer forms n+-type buried regions 73a, and the upper sublayer contains n-type collector regions 73e, p-type base regions 73d and n-type emitter regions 73c in the device regions 75.
The device regions 75 are laterally isolated by the SiO.sub.2 film 78 and vertically isolated by the underlying SiO.sub.2 layer 72 from each other.
The conventional SOI structure of FIG. 5 is fabricated by the following process steps:
First, the SOI structure having the substrate 71, the SiO.sub.2 layer 72 and the single-crystal Si layer 73 is prepared. The layer 73 has the n+-type lower sublayer 73a and the n-type upper sublayer 73b.
Then, after a thin Si.sub.3 N.sub.4 film 74 is formed on the Si layer 73, the Si layer 73 and the Si.sub.3 N.sub.4 film 74 are selectively removed by the popular photolithography and dry etching techniques, defining the device regions 75 and the non-device region 76 on the SiO.sub.2 layer 72, as shown in FIG. 7A. The Si.sub.3 N.sub.4 film 74 acts as an etching stop during this etching process.
Next, the thick SiO.sub.2 film 78 is deposited to cover the device regions 75 and the non-device region 76 over the substrate 71, as shown in FIG. 7B. The SiO.sub.2 film 78 is then polished to be flattened until the Si.sub.3 N.sub.4 film 74 is exposed, as shown in FIG. 7C. The film 74 act as a polishing stop in this process.
After removing the Si.sub.3 N.sub.4 film 74, the collector, base and emitter regions 73e, 73d and 73c are formed in the device regions 55 through the popular formation processes, providing the bipolar transistors in the regions 55. Thus, the semiconductor device shown in FIG. 5 is obtained.
The SOI structure of FIG. 5 can reduce the parasitic capacitances between the substrate 71 and the interconnecting conductors to (1/3) or (1/5) that of the structure of FIG. 3. However, a problem that the heat generated in the device regions 75 and the heat generated in the conductors radiates poorly, the reason of which is as follows:
The heat generated in the device regions 75 propagates to the substrate 71 and the SiO.sub.2 film 78 in the non-device region 76 along the arrows shown in FIG. 5. SiO.sub.2 has the thermal conductivity equal to about (1/100) the thermal conductivity of Si whose value is about 170 W/mK. Therefore, the heat does not propagate efficiently to the substrate 71 through the SiO.sub.2 film 78, which prevents the maximum available power consumption from increasing.
The SOI structure of FIG. 5 has another problem that some depressions 85 tend to be formed in the non-device region 76, as shown in FIG. 6, because the SiO.sub.2 film 78 is required to be polished excessively in consideration with the polishing rate fluctuation within the entire substrate 71. This problem becomes remarkably effective in the case of the island-like device regions 75 and of the extremely hard SiO.sub.2 layer 78, preventing the complete flatness.